1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
To reduce parasitic capacitance between wiring when fabricating semiconductor devices with multi-layered wiring structures on a semiconductor substrate, a low-dielectric-constant material has heretofore been used as the interlayer insulating film or air gaps (cavities) are formed between wiring.
The latter is disclosed, for example, in Japanese Patent Application Laid-open No. 85519/2001. In this publication, wirings having a reversed taper configuration on a sacrifice layer are formed made up of, for example, PSG (Phosphorous Silicate Glass) and the sacrifice layer is removed by dry etching or wet etching to thereby form air gaps between wirings.
Japanese Patent No. 3102382 discloses a semiconductor device and a method of manufacturing the same in which openings of via holes and opening between wirings are concurrently formed to form cavities on the insulating portions between the wirings.
However, in the conventional method wherein air gaps are formed after formation of the wirings, a mask of a photoresist film or the like is formed and interlayer insulating films between wirings are removed to form trench to form air gaps by means of etching. The use of a mask to form trenches to form air gap results in a significant increases in the number of processes.
Unlike this, the removal of the interlayer insulating film by dry etching without forming a mask may damage the wirings.
Moreover, as shown in FIGS. 1A and 1B, if an interlayer insulating film 1 is selectively removed by wet etching without forming a mask, shape after the etching becomes difficult to control. When overetching results, as shown in FIG. 1A, the interlayer insulating film 1 having via holes formed therein becomes irregularly shaped, and thus the supporting leg for the wiring 5 or the interlayer insulating film 1 between the wirings 5 may disappear.
On the other hand, if underetching occurs after the interlayer insulating film 1 is selectively removed by wet etching, as shown in FIG. 1B, interlayer insulating film 6 in which air gaps 9 are to be formed may take the shape of irregular tapers. As a result, even if via holes are formed in the wirings 5 and of low filling-up capability (i, e, the recesses are difficult to be filled up) to deposit an interlayer insulating film 6 therein, uniform air gaps 9 cannot be obtained.
Further, the use of a low-dielectric-constant material as a interlayer insulating film often makes a difference in etching selectivity for the etchant between the interlayer insulating film and its underlying layer small. This requires for an etching stopper film to be formed between the interlayer insulating film and its underlying layer. This in turn deteriorates the adhesiveness between layers and increases the parasitic capacitance between wirings despite the use of the low-dielectric-constant material as the interlayer insulating film.